Technology is trending toward the development of smaller and higher performance integrated circuits. The assessment of device parameters from test wafers that accompany batches of wafers in processing can be wholly misleading as to the geometries that actually exist on individual integrated circuits and even on the individual wafers that contain the integrated circuits. Tests that are conventionally performed on test wafers can include, for example, process, continuity, and design rule checks as well as device charateristic tests (e.g., device leakage tests), gate oxide leakage current tests, or circuit characteristic tests. In particular, test structures formed on test wafers are not always equivalent to the structures utilized in the integrated circuits. Test wafers are often produced with abbreviated process conditions and often lack the critical dimensions utilized in the integrated circuits on wafers that are supposedly being tested.
Access to test wafer information can be expensive in both labor and material cost. Further, test wafer information is not specific to the wafer that includes integrated circuits as processed or the die subjected to packaging. Device parameters can undergo subtle changes during further processing such as reliability stress conditions such as “burn-in” or packaging. The test wafer does not typically undergo “burn-in” and is not subjected to the stresses of further processing. Often the changes in device parameters as a result of further processing are explained with second order parameters such as impedance or delay changes. No direct method of determining some of these parameters on a specific die is generally available.
Gate oxide leakage is one such parameter. Gate oxide leakage has become an important process and design parameter as integrated circuits scale to smaller dimensions. Gate oxide leakage for older manufacturing technologies with about a 60 Å thick oxide were below about 1×10−15 amperes per square micron with 3.3 V bias across the oxide. Current manufacturing technologies with 16 Å of gate oxide, however, have shown measured leakages of about 4×10−8 amperes per square micron with a bias voltage of about one volt. From a different perspective, it has been reported that leakage from a 0.13 micron technology constitutes about 15% of core power in contrast to over 50% of the core power for a 0.09 micron technology in designs in excess of two million transistors.
The increase in device leakage with die sizing remaining the same adds to the increase in chip power consumption and design restrictions for scaled processes. Previously, chip power consumption consisted primarily of the charging and discharging of internally and externally connected capacitance. In aggregate, the junction leakage component was small enough to be neglected compared to the dynamic or AC power dissipation in older designs.
Typical process monitors for gate oxide leakage consist of a gate oxide grown over a large area on an otherwise, unprocessed wafer. Measureable leakage currents on a large area capacitor can be obtained using a shielded low current ammeter, which would otherwise be unobtainable from a single transistor. The leakage current process monitors, for reasons of economy, are not processed with the full compliment of processing steps, (e.g., implants or top metal layers). The leakage currents measured with process monitors may be conservative in that strain effects are not present. The leakage value may be excessive, representing single defects in the large area capacitor of the die independent of the test monitor.
There is a large variation in leakage currents from wafer to wafer and from batch to batch as a result of variations in defect levels and process conditions. Variations may occur at different locations on single wafers. Therefore, utilizing a whole wafer to provide leakage current and extrapolating that data over each integrated circuit in a batch of wafers is often unreliable and misleading.
Product reliability is often associated with single defect failures. Current products processed with thin gate oxides have witnessed increases in power consumption, thus increasing the temperature of the chip and thereby degrading speed performance. Identification of the source of the power increase is essential for reliability analysis. A method of improving the reliability of components is to subject them to stress testing or “burn-in.” “Burn-in” consists of applying a maximum voltage across the oxide or junction at an elevated temperature. Increases in leakage currents after “burn-in” have been measured on weak or defective components.
Some present methods of measuring gate oxide leakage usually involves probing wafers with large area MOS test devices. These MOS devices are not necessarily representative of gate structures actually found on integrated circuits. The large-area MOS test structures are not on the same wafer processed with the integrated circuits. Consequently, values of leakage currents obtained by these test structures are not necessarily representative of the actual leakage current exhibited by devices produced by the technology.
The reliability of devices suffers as a result of thin gate oxides. Reliability testing, or “burn-in,” is expensive both in labor and equipment costs. “Burn-in” includes stressing the integrated circuit with maximum voltage at high temperatures for short periods of time. Failures may occur from other than increases in gate oxide leakage, in which case it can be difficult to identify failure modes.
Therefore, there is a need for better device parameter measurements. Additionally, there is a need for device parameter measurements that can test parameters associated with an integrated circuit before and after processes such as “burn-in” or chip packaging.